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Volumn 31, Issue 11-12, 2000, Pages 991-998

General method in synthesis of pass-transistor circuits

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; ELECTRIC NETWORK TOPOLOGY; LOGIC CIRCUITS;

EID: 0034502029     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2692(00)00088-4     Document Type: Article
Times cited : (58)

References (10)
  • 1
    • 0032218681 scopus 로고    scopus 로고
    • A survey for pass-transistor logic technologies - Recent researches and developments and future prospects
    • Feb.
    • K. Taki, A survey for pass-transistor logic technologies - Recent researches and developments and future prospects, Proceedings of the ASP-DAC'98 Asian and South Pacific Design Automation Conference, Feb. 1998, pp. 223-226.
    • (1998) Proceedings of the ASP-DAC'98 Asian and South Pacific Design Automation Conference , pp. 223-226
    • Taki, K.1
  • 5
    • 85031541967 scopus 로고
    • 1.5 ns CMOS 16×16 multiplier using complementary pass-transistor logic
    • Suzuki M., et al. 1.5 ns CMOS 16×16 multiplier using complementary pass-transistor logic. IEEE Journal of Solid-State Circuits. 28:(11):1993;599-602.
    • (1993) IEEE Journal of Solid-State Circuits , vol.28 , Issue.11 , pp. 599-602
    • Suzuki, M.1
  • 7
    • 0025419522 scopus 로고
    • 3.8 ns CMOS 16×16-b multiplier using complementary pass-transistor logic
    • Yano K., et al. 3.8 ns CMOS 16×16-b multiplier using complementary pass-transistor logic. IEEE Journal of Solid-State Circuits. 25:(2):1990;388-395.
    • (1990) IEEE Journal of Solid-State Circuits , vol.25 , Issue.2 , pp. 388-395
    • Yano, K.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.