Wafer-level defect screening for big-D/small-A mixed-signal SoCs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 17, Issue 4, 2009, Pages 587-592

  Bahukudumbi, Sudarshan ^a   Ozev, Sule ^b   Chakrabarty, Krishnendu ^a   Iyengar, Vikram ^c  

^a Duke University   (United States)

^b Arizona State University   (United States)

^c IBM MICROELECTRONICS   (United States)

Author keywords

Cost model; Defect screening; Mixed signal; Signature analysis; System on chip (SoC) test; Wafer sort

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CHIP SCALE PACKAGES; CONSUMER ELECTRONICS; COST ACCOUNTING; COST REDUCTION; DEFECTS; ELECTRIC SIGNAL SYSTEMS; INTEGRATED CIRCUITS; PROGRAMMABLE LOGIC CONTROLLERS; QUERY PROCESSING; TESTING; VECTOR QUANTIZATION;

COST MODEL; MIXED-SIGNAL; SIGNATURE ANALYSIS; SYSTEM-ON-CHIP (SOC) TEST; WAFER SORT;

COST BENEFIT ANALYSIS;

EID: 62949228993     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.2006075     Document Type: Article

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