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Volumn , Issue , 2002, Pages 370-374

Noise -Its sources, and impact on design and test of mixed signal circuits

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC SIGNAL SYSTEMS; HETEROJUNCTION BIPOLAR TRANSISTORS; INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUITS;

EID: 84931028507     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DELTA.2002.994652     Document Type: Conference Paper
Times cited : (2)

References (10)
  • 2
    • 0033707515 scopus 로고    scopus 로고
    • Measurement and analysis of substrate noise waveform in mixed-signal ic environment
    • June
    • M. Nagata et.al.,.Measurement and Analysis of Substrate Noise Waveform in Mixed-Signal IC Environment. IEEE Trans on CAD of Integrated Circuits and Systems, June 2000
    • (2000) IEEE Trans on CAD of Integrated Circuits and Systems
    • Nagata, M.1
  • 3
    • 0030110603 scopus 로고    scopus 로고
    • Verification techniques for substrate noise and their application to mixed-signal ic design
    • March
    • N.K. Vergese et.al.,.Verification Techniques for Substrate noise and their application to Mixed-Signal IC Design. IEEE J. Solid-State Circuits, pp 354-365, March 1996
    • (1996) IEEE J. Solid-State Circuits , pp. 354-365
    • Vergese, N.K.1
  • 4
    • 0031341419 scopus 로고    scopus 로고
    • Substrate crosstalk reduction using soi technology
    • Dec
    • J.P. Raskin et.al.,.Substrate Crosstalk Reduction Using SOI Technology. IEEE Trans. on Electron Devices, pp 2252-2261 Dec 1997
    • (1997) IEEE Trans. on Electron Devices , pp. 2252-2261
    • Raskin, J.P.1
  • 5
    • 0032597766 scopus 로고
    • An overview of substrate coupling issues and modeling strategies
    • R. Singh,.An Overview of Substrate Coupling issues and modeling strategies. Proc. CICC. 1988, pp 491-498
    • (1988) Proc. CICC , pp. 491-498
    • Singh, R.1
  • 6
    • 0030110592 scopus 로고    scopus 로고
    • Modeling and analysis of substrate coupling in ic
    • March
    • R. Gharpurey, R. Meyer,.Modeling and Analysis of Substrate Coupling in IC. IEEE J. Solid-State Circuits, pp 344-353, March 1996
    • (1996) IEEE J. Solid-State Circuits , pp. 344-353
    • Gharpurey, R.1    Meyer, R.2
  • 7
    • 0033703261 scopus 로고    scopus 로고
    • A scalable substrate noise coupling model for design of mixed-signal ics
    • June
    • A. Samadevan et.al.,.A Scalable Substrate Noise Coupling Model for Design of Mixed-Signal ICs. IEEE J. Solid-State Circuits, June 2000
    • (2000) IEEE J. Solid-State Circuits
    • Samadevan, A.1
  • 9
    • 0035274508 scopus 로고    scopus 로고
    • Physical design guides for substrate noise reduction in cmos digital circuits
    • March
    • M. Nagata, et. al.,.Physical Design Guides for Substrate Noise Reduction in CMOS Digital Circuits., IEEE J. of Solid-State Circuits, Vol. 36, No.3, March 2001
    • (2001) IEEE J. of Solid-State Circuits , vol.36 , Issue.3
    • Nagata, M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.