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Volumn , Issue , 2003, Pages 512-519

Challenges in Low Cost Test Approach for ARM9™ Core Based Mixed-Signal SoC Dragon Ball™-MX1

(1)  Bao, George a  

a NONE

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; EMBEDDED SYSTEMS; JITTER; SPURIOUS SIGNAL NOISE;

EID: 0142246915     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (6)

References (20)
  • 1
    • 0142174860 scopus 로고    scopus 로고
    • MC9328MX1 Integrated Portable System Processor User's Manual
    • "MC9328MX1 Integrated Portable System Processor User's Manual", Motorola SPS Asia Pacific, 2002.
    • (2002) Motorola SPS Asia Pacific
  • 3
    • 0033353560 scopus 로고    scopus 로고
    • Applications of Semiconductor Test Economics and Multisite Testing to Lower Cost of Test
    • A.C.Evans, "Applications of Semiconductor Test Economics and Multisite Testing to Lower Cost of Test," IEEE International Test Conference, pp.113-123, 1999.
    • (1999) IEEE International Test Conference , pp. 113-123
    • Evans, A.C.1
  • 9
    • 0033742117 scopus 로고    scopus 로고
    • Extraction of Peak-to-peak and RMS Sinusoidal Jitter Using an Analytic Signal Method
    • Montreal, Canada, May
    • T.J. Yamaguchi, M. Soma, M. Ishida, T. Watanabe and T. Ohmi, "Extraction of Peak-to-peak and RMS Sinusoidal Jitter Using an Analytic Signal Method", Proc. IEEE VLSI Test Symposium, Montreal, Canada, May, 2000.
    • (2000) Proc. IEEE VLSI Test Symposium
    • Yamaguchi, T.J.1    Soma, M.2    Ishida, M.3    Watanabe, T.4    Ohmi, T.5
  • 12
    • 0032307605 scopus 로고    scopus 로고
    • Measuring Jitter of High Speed Data Channels Using Undersampling Techniques
    • Wajih Dalal and Daniel Rosenthal, "Measuring Jitter of High Speed Data Channels Using Undersampling Techniques", IEEE International Test Conference, 1998.
    • (1998) IEEE International Test Conference
    • Dalal, W.1    Rosenthal, D.2
  • 14
    • 0035687719 scopus 로고    scopus 로고
    • Test Evaluation and Data on Defect-Oriented BIST Architecture for High-Speed PLL
    • Seongwon Kim and Mani Soma, "Test Evaluation and Data on Defect-Oriented BIST Architecture for High-Speed PLL", IEEE International Test Conference, 2001.
    • (2001) IEEE International Test Conference
    • Kim, S.1    Soma, M.2
  • 15
  • 16
    • 0032315580 scopus 로고    scopus 로고
    • Stimulus Generation for Built-in-Self-Test of Charge-Pump Phase-Looked Loops
    • Benoit R. Veillette and Gordon W. Roberts, "Stimulus Generation for Built-In-Self-Test of Charge-Pump Phase-Looked Loops", IEEE International Test Conference, 1998.
    • (1998) IEEE International Test Conference
    • Veillette, B.R.1    Roberts, G.W.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.