Test planning for mixed-signal SOCs with wrapped analog cores

Proceedings -Design, Automation and Test in Europe, DATE '05

Volumn I, Issue , 2005, Pages 50-55

  Sehgal, Anuja ^a   Liu, Fang ^a   Ozev, Sule ^a   Chakrabarty, Krishnendu ^a  

^a Duke University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; COMPUTER SIMULATION; EMBEDDED SYSTEMS; HEURISTIC METHODS; OPTIMIZATION; SCHEDULING;

ANALOG WRAPPERS; DIGITAL CORES; MIXED-SIGNAL; SYSTEM-ON-CHIP; TEST ACCESS MECHANISM (TAM);

MICROPROCESSOR CHIPS;

EID: 33646919808     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.303     Document Type: Conference Paper

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