A wafer-level defect screening technique to reduce test and packaging costs for "big-D/small-A" mixed-signal SoCs

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2007, Pages 823-828

  Bahukudumbi, Sudarshan ^a   Ozev, Sule ^a   Chakrabarty, Krishnendu ^a   Iyengar, Vikram ^b  

^a Duke University   (United States)

^b IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; COST ACCOUNTING; COST REDUCTION; DEFECTS; ELECTRIC SIGNAL SYSTEMS; ELECTRONICS PACKAGING; PROGRAMMABLE LOGIC CONTROLLERS; SYSTEM-ON-CHIP;

CONSUMER ELECTRONICS MARKETS; MIXED SIGNAL SYSTEM ON CHIPS; MIXED-SIGNAL CORES; MIXED-SIGNAL TEST; NEW CORRELATIONS; SCREENING TECHNIQUES; SIGNATURE ANALYSIS; WAFER LEVEL TESTING;

COST BENEFIT ANALYSIS;

EID: 46649108345     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2007.358091     Document Type: Conference Paper

References (25)

1. R Brederlow et al., "A mixed-signal design roadmap," IEEE Design & Test, vol. 18, pp. 34-46, Nov. 2001.
2. tm-MX1," in Proc. ITC, 2003, pp. 512-519.
3. International Technology Roadmap for Semiconductors: Assembly and Packaging, http://www.itrs.net/Links/2005ITRS/AP2005.pdf, 2005.
4. A. B. Kahng, "The road ahead: The significance of packaging," IEEE Design & Test, vol. 19, pp. 104-105, Nov. 2002.
5. B. Koupal and T. Lee and B. Gravens. Bluetooth Single Chip Radios: Holy Grail or White Elephant, http://www.signiatech.com/pdf/paper_two_chip.pdf.
6. C. Pan and K. Cheng, "Pseudo-random testing and signature analysis for mixed-signal circuits," in Proc. ICCAD, 1995, pp. 102-107.
7. C. Taillefer and G. Roberts, "Reducing measurement uncertainty in a DSP-based mixed-signal test environment without increasing test time," IEEE Trans. VLSI Systems, vol. 13, pp. 862-861, Jul. 2005.
8. M. Bushnell and V. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits. Kluwer, 2000.
9. S. Bhattacharya and A. Chatterjee, "Optimized wafer-probe and assembled package test design for analog circuits," ACM Trans. Design Automation of Electronic Systems, vol. 10, pp. 303-329, Apr. 2005.
10. J. Sweeney and A. Tsefrekas, "Reducing test cost through the use of digital testers for analog tests," in Proc. ITC, 2005, pp. 1-9.
11. W. Lau, "Measurement challenges for on-wafer RF-SOC test," in Proc. Electronics Manufacturing Tech. Symp., 2002, pp. 353-359.
12. P. C. Maxwell, "Wafer-package test mix for optimal defect detection and test time savings," IEEE Design &Test of Computers, vol. 20, pp. 84-89, Sep. 2003.
13. W. R. Daasch et al., "Neighbor selection for variance reduction in IDDQ and other parametric data," in Proc. ITC, 2001, pp. 1240-1249.
14. A Keshavarzi et al., "Multiple-parameter CMOS IC testing with increased sensitivity for IDDQ," IEEE Trans. VLSI Sys., vol. 11, pp. 863-870, Oct. 2003.
15. S. Bernard et al., "A new methodology for ADC test flow optimization," in Proc. ITC, 2003, pp. 201-209.
16. A. Frisch and T. Almy, "HABIST: histogram based analog built in self test," in Proc. ITC, 1997, pp. 760-767.
17. E. Acar and S. Ozev, "Delayed-RF based test development for FM transceivers using signature analysis," in Proc. ITC, 2004, pp. 783-792.
18. M. d'Abreu, "Noise - its sources, and impact on design and test of mixed signal circuits," in Proc. Workshop on Electronic Design, Test and Applications, 1997, pp. 370-374.
19. U. Ingelsson et al., "Test scheduling for modular SOCs in an abort-on-fail environment," in Proc. ETS, 2005, pp. 8-13.
20. D. E. Becker and A. Sandborn, "On the use of yielded cost in modeling electronic assembly processes," IEEE Trans. Electronics Packaging Manufacturing, vol. 24, pp. 195-202, Jul. 2001.
21. S. Edbom and E. Larsson, "An integrated technique for test vector selection and test scheduling under test time constraint," in Proc. ATS, 2004, pp. 254-257.
22. ASICs Test Methodology, IBM Microelectronics, Essex Jet, VT 05452.
23. G. Chen et al, "Procedures for identifying untestable and redundant transition faults in synchronous sequential circuits," in Proc. ICCD, 2003, pp. 36-41.
24. http://www.mosis.org.
25. M. Shen et al., "Cost and performance analysis for mixed-signal system implementation: System-on-chip or system-on-package," IEEE Trans. Electronics Packaging Manufacturing, vol. 25, pp. 522-545, Oct. 2002.