Algorithms for state restoration and trace-signal selection for data acquisition in silicon debug

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 28, Issue 2, 2009, Pages 285-297

  Ko, Ho Fai ^a   Nicolici, Nicola ^a  

^a MCMASTER UNIVERSITY   (Canada)

Author keywords

Embedded logic analysis; Silicon debug; State restoration; Trace signal selection

Indexed keywords

DIGITAL CIRCUITS; DIGITAL INTEGRATED CIRCUITS; ELECTRIC NETWORK ANALYSIS; INTEGRATED CIRCUITS; NONMETALS; REPAIR; RESTORATION; TRACE ANALYSIS;

A-PRIORI; AUTOMATED SELECTIONS; CIRCUIT STATE; DESIGN ERRORS; EMBEDDED LOGIC ANALYSIS; IN-SYSTEM DEBUG; INTERNAL SIGNALS; ON-CHIP STORAGES; REAL TIME; SILICON DEBUG; STATE RESTORATION; TRACE-SIGNAL SELECTION;

LOGIC CIRCUITS;

EID: 59049104593     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2008.2009158     Document Type: Article

References (32)

1. H. F. Ko and N. Nicolici, "Automated trace signals identification and state restoration for improving observability in post-silicon validation," in Proc. IEEE/ACM Des. Autom. Test Eur., 2008, pp. 1298-1303.
2. W. K. Lam, Hardware Design Verification: Simulation and Formal Method-Based Approaches, Englewood Cliffs, NJ: Prentice-Hall, 2005.
3. M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits. Boston, MA: Kluwer, 2000.
4. B. Vermeulen and S. K. Goel, "Design for debug: Catching design errors in digital chips," IEEE Des. Test Comput., vol. 19, no. 3, pp. 35-43, May 2002.
5. H. Balachandran, K. Butler, and N. Simpson, "Facilitating rapid first silicon debug," in Proc. IEEE Int. Test Conf., Oct. 2002, pp. 628-637.
6. B. Vermeulen, "Special session: Why doesn't my system work?" in Proc. 43rd IEEE/ACM Des. Autom. Conf., 2006.
7. M. Abramovici, "Experience and opinion (design for debug)," in Proc. IEEE Int. Workshop Silicon Debug Diagnosis, 2006.
8. A. Khoche and D. Conti, "TRP in action: Embedded instrumentation in FPGAs," in Proc. 24th IEEE VLSI Test Symp., 2006, pp. 152-153. session 4C.
9. N. Nataraj, T. Lundquist, and K. Shah, "Fault localization using time resolved photon emission and STIL waveforms," in Proc. IEEE Int. Test Conf., Sep. 2003, pp. 254-263.
10. M. Abramovici, P. Bradley, K. Dwarakanath, P. Levin, G. Memmi, and D. Miller, "A reconfigurable design-for-debug infrastructure for SoCs," in Proc. IEEE/ACM Des. Autom. Conf., 2006, pp. 7-12.
11. ARM Limited, Embedded Trace Macrocells, Apr. 2007. [Online], Available: http://www.arm.com/products/solutions/ETM.html
12. P. Dahlgren, P. Dickinson, and I. Parulkar, "Latch divergency in microprocessor failure analysis," in Proc. IEEE Int. Test Conf., 2003, pp. 755-763.
13. O. Caty, P. Dahlgren, and I. Bayraktaroglu. "Microprocessor silicon debug based on failure propagation tracing," in Proc. IEEE Int. Test Conf., 2005, pp. 284-293.
14. G. Van Rootselaar and B. Vermeulen, "Silicon debug: Scan chains alone are not enough," in Proc. IEEE Int. Test Conf., 1999, pp. 892-902.
15. D. Josephson, "The manic depression of microprocessor debug," in Proc. IEEE Int. Test Conf., Oct. 2002, pp. 657-663.
16. D. Josephson and B. Gottlieb, "The crazy mixed up world of silicon debug," in Proc. IEEE Custom Integr. Circuits Conf., 2004, pp. 665-670.
17. C. MacNamee and D. Heffernan, "Emerging on-chip debugging techniques for real-time embedded systems," IEE Comput. Control Eng. J., vol. 11, no. 6, pp. 295-303, Dec. 2000.
18. Altera Verification Tool, Signal Tap II Embedded Logic Analyzer, 2006. [Online]. Available: http://www.altera.com/products/software/products/ quartus2/verification/signaltap2/sig-index.html
19. Xilinx Verification Tool, ChipScope Pro, 2006. [Online]. Available: http://www.xilinx.com/ise/optional-prod/cspro.htm
20. K. Morris, "On-chip debugging-Built-in logic analyzers on your FPGA," J. FPGA Structured ASIC, vol. 2, no. 3, Jan. 2004.
21. S. Sarangi, S. Narayanasamy, B. Caracal, A. Tiwari, B. Calder, and J. Torrellas, "Patching processor design errors with programmable hardware," IEEE Micro-Special Issue: Micro's Top Picks from Computer Architecture Conferences, vol. 27, no. 1, pp. 12-25, Jan./Feb. 2007.
22. M. Riley and M. Genden, "Cell broadband engine debugging for unknown events," IEEE Des. Test Comput., vol. 24, no. 5, pp. 486-493, Sep./Oct. 2007.
23. R. Leafherman and N. Stollon, "An embedding debugging architecture for SOCs," IEEE Potentials, vol. 24, no. 1, pp. 12-16, Feb./Mar. 2005.
24. A. Mayer, H. Siebert, and K. McDonald-Maier, "Boosting debugging support for complex systems on chip," Computer, vol. 40, no. 4, pp. 76-81, Apr. 2007.
25. M. Burtscher, I. Ganusov, S. Jackson, J. Ke, P. Ratanaworabhan, and N. Sam, "The VPC trace-compression algorithms," IEEE Trans. Comput., vol. 54, no. 11, pp. 1329-1344, Nov. 2005.
26. E. Anis and N. Nicolici, "On using lossless compression of debug data in embedded logic analysis," in Proc. IEEE Int. Test Conf., 2007, pp. 1-10.
27. E. Anis and N. Nicolici, "Low cost debug architecture using lossy compression for silicon debug," in Proc. IEEE/ACM Des. Autom. Test Eur., 2007, pp. 1-6.
28. Y.-C. Hsu, F. Tsai, W. Jong, and Y.-T. Chang, "Visibility enhancement for silicon debug," in Proc. IEEE/ACM Des. Autom. Conf., 2006, pp. 13-18.
29. J. Huang, C. James, and D. Walker, VLSI Test Principles and Architectures: Design for Testability. New York: Academic, 2006.
30. G. D. Micheli, Synthesis and Optimization of Digital Circuits. New York: McGraw-Hill, 1994.
31. L. H. Goldstein, "Controllability/observability analysis of digital circuits," IEEE Trans. Circuits Syst., vol. CAS-26, no. 9, pp. 685-693, Sep. 1979.
32. F. Brglez, D. Bryan, and K. Kozminski, "Combinational profiles of sequential benchmark circuits," in Proc. IEEE Int. Symp. Circuits Syst., 1989, pp. 1929-1934.