SCOPUS 정보 검색 플랫폼

Volumn 19, Issue 3, 2002, Pages 37-45

Design for debug: Catching design errors in digital chips

(2) Vermeulen, Bart a Goel, Sandeep Kumar a

a PHILIPS RESEARCH LABORATORIES (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; COMPUTER SOFTWARE; DIGITAL INTEGRATED CIRCUITS; DYNAMIC RANDOM ACCESS STORAGE; ELECTRIC NETWORK ANALYSIS; ERROR DETECTION; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT TESTING; INTERFACES (COMPUTER); MICROPROCESSOR CHIPS; SILICON WAFERS;

CIRCUIT DEBUGGING; DESIGN OF DEBUG; STATIC TIMING ANALYSIS; TEST ACCESS PORT;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036575031 PISSN: 07407475 EISSN: None Source Type: Journal
DOI: None Document Type: Article

Times cited : (99)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.