Facilitating rapid first silicon debug

IEEE International Test Conference (TC)

Volumn , Issue , 2002, Pages 628-637

  Balanchandran, Hari ^a   Butler, Kenneth M ^a   Simpson, Neil ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; DATA ACQUISITION; DATA REDUCTION; DATABASE SYSTEMS; DESIGN FOR TESTABILITY; FAILURE ANALYSIS; LOGIC CIRCUITS; RELIABILITY; SEMICONDUCTING SILICON;

DESIGN FOR PRODUCTIZATION; DESIGN IN EXCELLENCE; FAULT GRADING; SILICON DEBUG; TEST PATTERN TRACKING TECHNIQUE;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036446701     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)

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2. T. L. McLaurin and F. Frederick, "The Testability Features of the MCF5407 Containing the 4th Generation COLDFIRE Microprocessor Core," in Proc. 2000 IEEE Int. Test Conf., pp. 151-159, Oct., 2000.
3. E. B. Eichelberger and T. W. Williams, "A Logic Design Structure for LSI Testability," in Proc. 14th ACM/IEEE Design Auto. Conf., pp. 462-468, June. 1977
4. B. Pouya and A. L. Crouch, "Optimization Trade-offs for Vector Volume and Test Power," in Proc. 2000 IEEE Int. Test Conf., pp. 873-881, Oct., 2000.
5. J. Saxena, K. M. Butler, and L. Whetsel, "An Analysis of Power Reduction Techniques in Scan Testing," in Proc. 2001 IEEE Int. Test Conf., pp. 670-677, Oct.-Nov., 2001.
6. C. Force and T. Austin, "Testing the Design: The Evolution of Test Simulation," in Proc. 1998 Int. Test Conf., pp. 612-621, Oct., 1998.
7. Farida Rajkotwala, Personal communication with Agilent Test and Measurement Applications Engineer.
8. J. Kharer et al., "Key attributes of an SRAM Testing Strategy Required for Effective Process Monitoring", Proc. Of 1993 IEEE Workshop on Memory Testing, pp. 1-6.
9. A. D. J. Van De Goor, "Using March Tests to Test SRAMs", IEEE Design and Test of Computers, 1993, pp. 8-14.
10. D. Wilson, A. J. Walton, "Automatic In-Line Measurement for the Identification of Killer Defects", Proc. Of 1994 ICMTS.
11. Hari Balachandran, Jason Parker, Daniel Shupp, Stephanie Butler, Kenneth M. Butler, Craig Force, Jason Smith, "Correlation of Logical Failures to a Suspect Process Step." In Proc. 1999 Int. Test Conf.
12. K. M. Butler et al., "Automated Diagnosis in Testing and Failure Analysis", IEEE Design & Test of Computers, 1997, pp. 83-89.
13. H. Balachandran et al, "Expediting Ramp-to-Volume Production", to appear in the Proc. Of 1999 Int'l Test Conference.
14. A. Kinra et al, "Diagnostic techniques for the UltraSPARC™ Microprocessors", Proc. Of the 1998 IEEE Int'l Test Conference, pp. 480-486.
15. C. M. Li and E. J. McCluskey, "Testing for Tunneling Opens," in Proc. 2000 IEEE Int. Test Conf., 85-94, Oct., 2000.