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Volumn , Issue , 2005, Pages 548-553

Clock trees: Differential or single ended?

Author keywords

[No Author keywords available]

Indexed keywords

90 NM TECHNOLOGY; CLOCK DISTRIBUTION; CLOCK TREE; LOW SWING; MANUFACTURING VARIATION; POWER-SUPPLY NOISE; SINGLE-ENDED; TEST CHIPS;

EID: 34547241854     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2005.31     Document Type: Conference Paper
Times cited : (8)

References (13)
  • 1
    • 0035334849 scopus 로고    scopus 로고
    • A clock distribution for microprocessors
    • May
    • P. Restle, et al-"A clock distribution for microprocessors", IEEE J. Solid State Circuits, May 2001, pp. 792-799
    • (2001) IEEE J. Solid State Circuits , pp. 792-799
    • Restle, P.1
  • 2
    • 2442641705 scopus 로고    scopus 로고
    • Timing uncertainty measurements on the Power 5 microprocessor
    • P. Restle, et al-"Timing uncertainty measurements on the Power 5 microprocessor", Proc. ISSCC'04, pp. 354-355
    • Proc. ISSCC'04 , pp. 354-355
    • Restle, P.1
  • 3
    • 0036112361 scopus 로고    scopus 로고
    • The core clock system on the next generation Itanium processor
    • F. Anderson, et al-"The core clock system on the next generation Itanium processor", Proc. ISSCC '02, pp. 146-147
    • Proc. ISSCC '02 , pp. 146-147
    • Anderson, F.1
  • 4
    • 0141649526 scopus 로고    scopus 로고
    • Clock generation and distribution for the third generation itanium processor
    • S. Tam, et al-"Clock generation and distribution for the Third Generation Itanium Processor", Proc. 2003 Symposium on VLSI Circuits, pp.9-12
    • Proc. 2003 Symposium on VLSI Circuits , pp. 9-12
    • Tam, S.1
  • 6
    • 84886711401 scopus 로고    scopus 로고
    • The clock distribution for the Power 4 microprocessor
    • P. Restle, et al-"The clock distribution for the Power 4 microprocessor", Proc. ISSCC'02, pp. 144-146
    • Proc. ISSCC'02 , pp. 144-146
    • Restle, P.1
  • 7
    • 85001134901 scopus 로고    scopus 로고
    • Technology scaling impact of variation on clock skew and wire delay
    • V. Mehrotra, et al-"Technology scaling impact of variation on clock skew and wire delay", Proc. IITC '01, pp. 122-124
    • Proc. IITC '01 , pp. 122-124
    • Mehrotra, V.1
  • 8
    • 84886712254 scopus 로고    scopus 로고
    • A 4. 6 GHz resonant global clock distribution network
    • S. Chan, et al-"A 4.6 GHz resonant global clock distribution network", Slides from ISSCC'04
    • Slides from ISSCC'04
    • Chan, S.1
  • 9
    • 0035707479 scopus 로고    scopus 로고
    • Statistical clock skew with data delay variations
    • Dec
    • D. Harris, et al-"Statistical clock skew with data delay variations", IEEE Trans. VLSI systems, Dec. 2001, pp. 888-898
    • (2001) IEEE Trans. VLSI Systems , pp. 888-898
    • Harris, D.1
  • 10
    • 0035397883 scopus 로고    scopus 로고
    • Full wave PEEC time-domain method of modeling on-chip interconnects
    • July
    • P. Restle, et al-"Full wave PEEC time-domain method of modeling on-chip interconnects", IEEE Trans. CAD Circuits and Systems, July 2001, pp. 877-886
    • (2001) IEEE Trans. CAD Circuits and Systems , pp. 877-886
    • Restle, P.1
  • 11
    • 84886705690 scopus 로고    scopus 로고
    • www.iec.org/online/tutorials/low-voltage/
  • 12
    • 84886673002 scopus 로고    scopus 로고
    • Feasibility of monolithic and stacked 3D DC-DC converters for microprocessors in 90 nm generation
    • G. Schrom, et al-"Feasibility of monolithic and stacked 3D DC-DC converters for microprocessors in 90 nm generation ", Proc. ISLPED'04, pp. 263-269
    • Proc. ISLPED'04 , pp. 263-269
    • Schrom, G.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.