Adapting cache line size to application behavior

Proceedings of the International Conference on Supercomputing

Volumn , Issue , 1999, Pages 145-154

  Veidenbaum, Alexander V ^a   Tang, Weiyu ^a   Gupta, Rajesh ^a   Nicolau, Alexandru ^a   Ji, Xiaomei ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; MULTIPROCESSING SYSTEMS;

CACHE LINE SIZE;

BUFFER STORAGE;

EID: 0032645271     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/305138.305188     Document Type: Article

References (15)