Si nanowire CMOS transistors and circuits by top-down technology approach

ECS Transactions

Volumn 13, Issue 1, 2008, Pages 201-211

  Balasubramanian, N ^a   Singh, N ^a   Rustogi, S C ^a   Buddharaju, K D ^a   Fu, J ^b   Hui, Z ^b   Balakumar, S ^a   Agarwal, A ^a   Manhas, S K ^a   Lo, G Q ^a   Kwong, D L ^a  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

^b NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INVERTERS; CMOS SCALING; CMOS TRANSISTORS; DEVICE ARCHITECTURES; GATE LENGTHS; GE CONTENTS; IC INDUSTRIES; MANUFACTURING METHODS; OTHER APPLICATIONS; RING OSCILLATORS; ROADMAP; SI NANOWIRES; SIGE NANOWIRES; SONOS MEMORIES; STATIC CONTROLS; TECHNOLOGY PLATFORMS; TOP DOWNS;

DATA STORAGE EQUIPMENT; ELECTRIC WIRE; GALLIUM ALLOYS; GERMANIUM; INTEGRATED CIRCUITS; LITHOGRAPHY; LOGIC GATES; NANOSTRUCTURED MATERIALS; NANOSTRUCTURES; NANOWIRES; TRANSISTORS;

SILICON;

EID: 55649113711     PISSN: 19385862     EISSN: 19386737     Source Type: Conference Proceeding    
DOI: 10.1149/1.2911501     Document Type: Conference Paper

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