A gate delay model focusing on current fluctuation over wide-range of process and environmental variability

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2006, Pages 47-53

  Shinkai, Ken'ichi ^a   Hashimoto, Masanori ^a   Kurokawa, Atsushi ^b   Onoye, Takao ^a  

^a OSAKA UNIVERSITY   (Japan)

^b SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER   (Japan)

Author keywords

Gate delay model; Static timing analysis; Statistical timing analysis; Variability

Indexed keywords

DESIGN; MODAL ANALYSIS; STATIC ANALYSIS; STATISTICAL METHODS; STATISTICS; SYSTEMS ANALYSIS; TIME MEASUREMENT;

(E ,3E) PROCESS; 90 NM TECHNOLOGY; COMPUTER-AIDED DESIGN; CURRENT MODELING; DC ANALYSIS; ENVIRONMENTAL VARIABILITY; EXPERIMENTAL RESULTS; GATE DELAYS; INPUT TRANSITION; INTERNATIONAL CONFERENCES; ON CURRENT (ION); OUTPUT LOAD; PATH DELAY (PD); STATIC TIMING ANALYSIS (STA); STATISTICAL STATIC TIMING ANALYSIS (SSTA); STATISTICAL TIMING ANALYSIS; SUPPLY VOLTAGES; TEMPERATURE FLUCTUATIONS; TIMING ANALYSIS; UNDER GATE; WIDE-RANGE;

SENSITIVITY ANALYSIS;

EID: 46149122091     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2006.320086     Document Type: Conference Paper

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