The impact of back-end-of-line process variations on critical path timing

2006 International Interconnect Technology Conference, IITC

Volumn , Issue , 2006, Pages 193-195

  Nguyen Hoang, V ^a   Kumar, A ^a   Christie, P ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK ANALYSIS; NETWORKS (CIRCUITS); TECHNOLOGY; TIME MEASUREMENT;

BACK-END OF LINE; CRITICAL PATHS; DETRIMENTAL EFFECTS; INTERCONNECT GEOMETRY; INTERCONNECT RESISTANCE; INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE; LOW-POWER CIRCUITS; PROCESS VARIATIONS; SMALL VARIATIONS; SUB-100 NM; TECHNOLOGY NODES;

TIMING CIRCUITS;

EID: 50249091644     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2006.1648685     Document Type: Conference Paper

References (5)

1. W. Steinhoegl, G. Schindler, G. Steinlesberger, M. Traving, M. Engelhardt, in Proceedings of IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 3-5 Sept. 2003, Boston, MA, USA, p. 27 - 30, 2003
2. J. A. Davis, V. K. De, and J. D. Meindl. IEEE Trans. Electron Devices, 45(3), pp. 580-589, March 1998.
3. P. Christie. IEEE Trans, on VLSI, 9(6), pp. 913-921, December 2001.
4. M. Iqbal, A. Sharkawy, U. Hameed, and P. Christie, Proc. IEEE/ACM System Level Interconnect Prediction Workshop, pp. 91-96, March 2002, ACM Press.
5. V. Nguyen Hoang, P. Christie, A. Heringa, A. Kumar and R. Ng, Proceedings of IEEE International Interconnect Technology Conference (IITC), June 6-8, 2005, San Francisco, CA, USA, p. 191 - 193, 2005.