Zigzag super cut-off CMOS (ZSCCMOS) scheme with self-saturated virtual power lines for subthreshold-leakage-suppressed sub-1-V-VDDLSI's

European Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 679-682

  Min, Kyeong Sik ^a   Sakurai, Takayasu ^a  

^a INSTITUTE OF INDUSTRIAL SCIENCE   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

HIGH-VOLTAGE STRESS; RECOVERY TIME; SERIES-CONNECTED; TECHNOLOGY NODES; VIRTUAL POWER;

ELECTRIC LINES;

EID: 77954528295     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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9. Y. Nakagome et al., "Circuit techniques for 1.5-3.6-V battery-operated 64-Mb DRAM," IEEE-JSSC, vol. 26, pp. 1003-1010, July, 1991.