Coarse-grain MTCMOS sleep transistor sizing using delay budgeting

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2008, Pages 385-390

  Pakbaznia, Ehsan ^a   Pedram, Massoud ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY BUDGETING; LOGIC CELLS; MULTI-THRESHOLD CMOS; NEW APPROACHES; PARASITIC RESISTANCES; POWER GATING; SLEEP TRANSISTOR PLACEMENT; SLEEP TRANSISTORS; STAND-BY LEAKAGE; STANDARD CELLS; TIMING SLACK; UPPER BOUNDS; VIRTUAL GROUND;

BUDGET CONTROL; CHLORINE COMPOUNDS; CMOS INTEGRATED CIRCUITS; ELECTRIC BATTERIES; INDUSTRIAL ECONOMICS; INDUSTRIAL ENGINEERING; LEAKAGE CURRENTS; LOGIC DEVICES; NETWORKS (CIRCUITS); SLEEP RESEARCH; STANDARDS; SULFATE MINERALS; TESTING; TIMING CIRCUITS; VLSI CIRCUITS;

TRANSISTORS;

EID: 49749122099     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2008.4484711     Document Type: Conference Paper

References (9)

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