A low-cost serial decoder architecture for low-density parity-check convolutional codes

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 55, Issue 7, 2008, Pages 1967-1976

  Bates, Stephen ^a   Chen, Zhengang ^a   Gunthorpe, Logan ^a   Pusane, Ali Emre ^b   Zigangirov, Kamil Sh ^b   Costello Jr , Daniel J ^b  

^a UNIVERSITY OF ALBERTA   (Canada)

^b University of Notre Dame   (United States)

Author keywords

Convolutional codes (CCs); Data communication; Error correction codes; High speed integrated circuits

Indexed keywords

CONVOLUTION; COSTS; ERROR CORRECTION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); ITERATIVE DECODING; MEMORY ARCHITECTURE;

CONSTRAINT LENGTHS; DATA-COMMUNICATION; ERROR CORRECTION CODES; HIGH-SPEED INTEGRATED CIRCUITS; LOW DENSITY PARITY CHECK; MEMORY CONSUMPTION; NUMBER OF ITERATIONS; PROPOSED ARCHITECTURES;

CONVOLUTIONAL CODES;

EID: 50549090014     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2008.918002     Document Type: Article

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