A memory-based architecture for FPGA implementations of low-density parity-check convolutional decoders

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 336-339

  Bates, Stephen ^a   Block, Gary ^a  

^a UNIVERSITY OF ALBERTA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

COMMUNICATION APPLICATION; CONVOLUTIONAL DECODERS; DECODER ARCHITECTURE; DECODER IMPLEMENTATION; FPGA IMPLEMENTATIONS; LOW DENSITY PARITY CHECK; VOICE AND VIDEO;

CONVOLUTION; CONVOLUTIONAL CODES; DECODING; PACKET SWITCHING; SWITCHING NETWORKS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 67649118584     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1464593     Document Type: Conference Paper

References (9)

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