A 54 Mbps (3,6)-regular FPGA LDPC decoder

IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

Volumn , Issue , 2002, Pages 127-132

  Zhang, Tong ^a   Parhi, K K ^a  

^a University of Minnesota   (United States)

Author keywords

Application specific integrated circuits; AWGN channels; Bit error rate; Design methodology; Field programmable gate arrays; Hardware; Iterative decoding; Parity check codes; Routing; Throughput

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BIT ERROR RATE; CHANNEL CODING; CODES (SYMBOLS); COMPUTER HARDWARE; FORWARD ERROR CORRECTION; ITERATIVE DECODING; ITERATIVE METHODS; NOISE GENERATORS; SIGNAL PROCESSING; THROUGHPUT; WHITE NOISE;

AWGN CHANNEL; DECODER DESIGNS; DESIGN METHODOLOGY; LDPC DECODER; PARITY CHECK CODES; PARTLY PARALLELS; ROUTING; XILINX FPGA;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 84948953245     PISSN: 15206130     EISSN: None     Source Type: Journal    
DOI: 10.1109/SIPS.2002.1049697     Document Type: Article

References (6)

1. R. G. Gallager, Low-Density Parity-Check Codes, M.I.T. Press, 1963. available at http://justice.mit.edu/people/gallager.html.
2. D. J. C. MacKay, "Good error-correcting codes based on very sparse matrices," IEEE Transactions on Information Theory, vol. 45, pp. 399-431, Mar. 1999.
3. T. Zhang, Z. Wang, and K. K. Parhi, "On finite precision implementation of low-density parity-check codes decoder," in Proc. of 2001 IEEE Int. Symp. on Circuits and Systems, Sydney, May 2001. available at http://www.ece.umn.edu/groups/ddp/turbo/.
4. A. J. Blanksby and C. J. Howland, "A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder," IEEE Journal of Solid-State Circuits, vol. 37, no. 3, pp. 404-412, March 2002.
5. T. Zhang and K. K. Parhi, "VLSI implementation oriented (3, k)-regular low-density parity-check codes," IEEE Workshop on Signal Processing Systems (SiPS), Sept. 2001. available at http://www.ece.umn.edu/groups/ddp/turbo/.
6. T. Zhang and K. K. Parhi, "Joint code and decoder design for implementation-oriented (3, k)-regular ldpc codes," in Proc. of IEEE Asilomar Conference, Nov. 2001, pp. 1232-1236.