Architectures for ASIC Implementations of Low-Density Parity-Check Convolutional Encoders and Decoders

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 4513-4516

  Swamy, Ramkrishna ^a   Bates, Stephen ^a   Brandon, Tyler ^a  

^a UNIVERSITY OF ALBERTA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CONVOLUTIONAL ENCODERS; DECODER ARCHITECTURE; LOW DENSITY PARITY CHECK;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CONVOLUTION; CONVOLUTIONAL CODES; ELECTRIC POWER SUPPLIES TO APPARATUS; WATER WELL PUMPS;

DECODING;

EID: 67649122043     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465635     Document Type: Conference Paper

References (8)

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2. T. Zhang and K. Parhi, "A 54 MBPS (3,6)-regular FPGA LDPC decoder," in Proceedings of the IEEE Workshop on Signal Processing, 2002.
3. Z. C. S. Bates and X. Dong, "Low-density parity check convolutionalcodes for packet switching networks," Submitted to IEEE Communication Letters, 2004.
4. S. Bates and G. Block, "A memory-based architecture for FPGA implementations of low-density parity-check decoders," in Proceedings of IEEE Symposium on Circuits and Systems, 2005.
5. A. J. Felstr̈om and K. S. Zigangirov, "Time-varying periodic convolutional codes with low-density parity-check matrix," IEEE Trans. Information Theory, vol. 45, no. 6, September 1999.
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7. A. Sridharan and D. Costello, "A new construction method for low density parity check convolutional codes," in Proceedings of The IEEE Information Theory Workshop, 2002.
8. S. B. Z. Chen and X. Dong, "Performance of low-density parity-check convolutional codes," 2004, available from http://www.ece.ualberta.ca/ ~sbates.