FPGA based implementation of decoder for array low-density parity-check codes

ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

Volumn V, Issue , 2005, Pages

  Bhagawat, Pankaj ^a   Uppal, Momin ^a   Choi, Gwan ^a,b  

^a TEXAS A AND M UNIVERSITY   (United States)

^b IEEE

Author keywords

[No Author keywords available]

Indexed keywords

CODES (SYMBOLS); COMPUTATIONAL COMPLEXITY; FIELD PROGRAMMABLE GATE ARRAYS; PARALLEL PROCESSING SYSTEMS; PERFORMANCE;

LDPC CODES; LOW DENSITY PARITY CHECK (LDPC) CODES; PARALLELISM; XILINX FIELD PROGRAMMABLE GATE ARRAY (FPGA) DEVICE;

DECODING;

EID: 33646777145     PISSN: 15206149     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICASSP.2005.1416232     Document Type: Conference Paper

References (6)

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3. A. J. Blanksby and C.J. Howland, "A 690-mW 1-Gb/s 1024-b, Rate-1/2 Low-Density Parity-Check Code Decoder", IEEE J. Solid-State Circuits, Vol.37, 2002, pp. 404-412.
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5. E. Eleftheriou and S. Olcer, "Low density parity-check codes for digital subscriber lines", Proc. ICC'2002, New York, pp. 1752-1757(2002).
6. A. Selvarathinam, G. Choi, A. Prabhakar, K. Narayanan, and E. Kim, "A massively scaleable decoder architecture for low-density parity-check codes", Proceedings of International Symposium on Circuits and Systems, May 2003, vol.2, pp.61-64