Termination sequence generation circuits for low-density parity-check convolutional codes

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 53, Issue 9, 2006, Pages 1909-1917

  Bates, Stephen ^a   Elliott, Duncan G ^a   Swamy, Ramkrishna ^a  

^a UNIVERSITY OF ALBERTA   (Canada)

Author keywords

Coding and decoding; Data communication; Error correction codes; Linear algebra; Packet switching

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CODE CONVERTERS; CONVOLUTIONAL CODES; DECODING; ENCODING (SYMBOLS); ERROR CORRECTION; FIELD PROGRAMMABLE GATE ARRAYS; LINEAR ALGEBRA; SEQUENTIAL CIRCUITS;

LOW-DENSITY PARITY-CHECK CONVOLUTIONAL CODES; TERMINATION SEQUENCE GENERATION CIRCUITS;

DATA COMMUNICATION SYSTEMS;

EID: 33749386596     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2006.880313     Document Type: Article

References (16)

1. C. J. Howland and A. J. Blanksby, "A 690-mW 1-Gb/s 1024-b, rate 1/2 low density parity check decoder," IEEE J. Solid-State Circuits, vol. 37, no. 3, pp. 404-412, Mar. 2002.
2. T. Zhang and K. Parhi, "A 54 MBPS (3,6)-regular FPGA LDPC decoder," in Proc. IEEE Worksh. Signal Process., Oct. 2002, pp. 127-132.
3. P. Urard, E. Yeo, L. Oaumier, P. Georgelin, T. Michel, and V. Lebars, "A 135 mb/s DVB-S2 compliant CODEC based on 64,800b LDPC and BCH codes," in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC'05), Feb. 2005, pp. 446-447.
4. C. Schlegel and L. Perez, Trellis and Turbo Coding. New York: IEEE Press, 2004.
5. A. Jimenez-Felström and K. S. Zigangirov, "Time-varying periodic convolutional codes with low-density parity-check matrix," IEEE Trans. Inf. Theory, vol. 45, no. 6, pp. 2181-2191, Sep. 1999.
6. S. Bates, Z. Chen, and X. Dong, "Low-density parity check convolutional codes for Ethernet networks," in Proc. IEEE Pacific Rim Conf. Commun., Comput., Signal Process., Aug. 2005, pp. 86-91.
7. R. Swamy, S. Bates, and T. L. Brandon, "Architectures for ASIC implementations of low-density parity-check convolutional encoders and decoders," in Proc. IEEE Symp. Circuits Syst. (ISCAS), Kobe, Japan, 2005.
8. S. Bates and G. Block, "A memory based architecture for low-density parity-check convolutional decoders," in Proc. IEEE Symp. Circuits Syst. (ISCAS), Kobe, Japan, May 2005.
9. A. Sridharan and D. Costello, Jr., "A new construction method for low density parity check convolutional codes," in Proc. IEEE Inf. Theory Worksh., Oct. 2002, p. 212.
10. R. Tanner, D. Sridhara, A. Sridharan, T. Fuja, and D. Costello, Jr., "LDPC block and convolutional codes based on circulant matricies," IEEE Trans. Inf. Theory, vol. 50, no. 12, pp. 2966-2984, Dec. 2004.
11. A. Darabiha, A. C. Carusone, and F. R. Kschischang, "Multi-gbit/sec low density parity check decoders with reduced interconnect complexity," in Proc. IEEE Int. Symp. Circuits Syst., Kobe, Japan, May 2005.
12. D. J. C. Mackay, David Mackay's Web Encyclopedia of Sparse Graph Codes.
13. I. Djurdjevic, J. Xu, K. Abdel-Ghaffer, and S. Lin, "A class of low-density parity-check codes constructed based on Reed-Solomon codes with two information symbols," IEEE Commun. Lett., vol. 7, no. 7, pp. 317-319, Jul. 2003.
14. A. E. Pusane, A. Jimenez-Felström, A. A. Sridharan, M. M. Lentmaier, K. S. Zigangirov, and D. J. Costello, Jr., "Implementation aspects of LDPC convolutional codes," IEEE Trans. Commun., to be published.
15. T. J. Richardson and R. L. Urbanke, "Efficient encoding of low-density parity check codes," IEEE Trans. Inf. Theory, vol. 47, no. 2, pp. 638-656, Feb. 2001.
16. Z. Chen, S. Bates, and X. Dong, "Low-density parity-check convolutional codes applied to packet based communication systems," in Proc. IEEE Global Telecommun. Conf. (GLOBECOM'05), Nov. 2005.