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Volumn 1, Issue , 2003, Pages 113-117

A FPGA and ASIC Implementation of Rate 1/2, 8088-b Irregular Low Density Parity Check Decoder

Author keywords

[No Author keywords available]

Indexed keywords

IRREGULAR PARTITIONED PERMUTATION (IPP) METHOD; LOW DENSITY PARITY CHECK DECODERS; MEMORY MANAGEMENT;

EID: 0842310952     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (72)

References (9)
  • 1
    • 84925405668 scopus 로고
    • Low density parity check codes
    • R. G. Gallager, "Low density parity check codes," IRE Trans. Info. Theory, vol. IT-8, pp. 21-28, 1962.
    • (1962) IRE Trans. Info. Theory , vol.IT-8 , pp. 21-28
    • Gallager, R.G.1
  • 2
    • 0030219216 scopus 로고    scopus 로고
    • Near Shannon limit performance of low density parity check codes
    • D. J. C. MacKay and R. M. Neal, "Near Shannon limit performance of low density parity check codes," Electronics Letters, vol. 32, pp. 1645, 1996.
    • (1996) Electronics Letters , vol.32 , pp. 1645
    • MacKay, D.J.C.1    Neal, R.M.2
  • 3
    • 0035246127 scopus 로고    scopus 로고
    • Design of capacity approaching irregular low-densily parity-check codes
    • T. J. Richardson, M. A. Shokrollahi, and R. L. Urbanke, "Design of capacity approaching irregular low-densily parity-check codes," IEEE Trans. Inform. Theory, vol. 47, pp. 619-637, 2001.
    • (2001) IEEE Trans. Inform. Theory , vol.47 , pp. 619-637
    • Richardson, T.J.1    Shokrollahi, M.A.2    Urbanke, R.L.3
  • 4
    • 0036504121 scopus 로고    scopus 로고
    • A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder
    • A. J. Blanksby and C. J. Howland, "A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder," IEEE J. Solid-State Circuits, vol. 37, pp. 404-412, 2002.
    • (2002) IEEE J. Solid-state Circuits , vol.37 , pp. 404-412
    • Blanksby, A.J.1    Howland, C.J.2
  • 5
    • 84948953245 scopus 로고    scopus 로고
    • A 54 MBPS (3, 6)-regular FPGA LDPC decoder
    • T. Zhang and K. K. Parhi, "A 54 MBPS (3, 6)-regular FPGA LDPC decoder," IEEE Proc. of SIPS, pp. 127-132, 2002.
    • (2002) IEEE Proc. of SIPS , pp. 127-132
    • Zhang, T.1    Parhi, K.K.2
  • 6
    • 0037633661 scopus 로고    scopus 로고
    • LDPC code construction with flexible hardware implementation
    • D. Hocevar, "LDPC code construction with flexible hardware implementation," to appear in Proc. of ICC'03, 2003.
    • (2003) Proc. of ICC'03
    • Hocevar, D.1
  • 8
    • 0033698195 scopus 로고    scopus 로고
    • Evaluation of low-density parity-check codes over block fading channels
    • M. Chiani, A. Conti, and A. Ventura, "Evaluation of low-density parity-check codes over block fading channels," Proc. ICC, vol. 3, pp. 1183-1187, 2000.
    • (2000) Proc. ICC , vol.3 , pp. 1183-1187
    • Chiani, M.1    Conti, A.2    Ventura, A.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.