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Volumn 1, Issue , 2003, Pages 113-117
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A FPGA and ASIC Implementation of Rate 1/2, 8088-b Irregular Low Density Parity Check Decoder
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Author keywords
[No Author keywords available]
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Indexed keywords
IRREGULAR PARTITIONED PERMUTATION (IPP) METHOD;
LOW DENSITY PARITY CHECK DECODERS;
MEMORY MANAGEMENT;
ALGORITHMS;
APPLICATION SPECIFIC INTEGRATED CIRCUITS;
FIELD PROGRAMMABLE GATE ARRAYS;
ITERATIVE METHODS;
MATRIX ALGEBRA;
ROUTERS;
TABLE LOOKUP;
DECODING;
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EID: 0842310952
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (72)
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References (9)
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