Scalable defect mapping and configuration of memory-based nanofabrics

Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

Volumn 2005, Issue , 2005, Pages 11-18

  He, Chen ^a,b   Jacome, Margarida F ^a   De Veciana, Gustavo ^a  

^a The University of Texas at Austin   (United States)

^b FREESCALE SEMICONDUCTOR INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MEMORY-BASED NANOFABRICS; NANOSYSTEMS; TRIPLEMODULE-REDUNDANCY (TMR) TESTS;

BENCHMARKING; COMPUTATIONAL METHODS; FAULT TOLERANT COMPUTER SYSTEMS; NANOTECHNOLOGY; REDUNDANCY;

SHAPE MEMORY EFFECT;

EID: 33846635051     PISSN: 15526674     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HLDVT.2005.1568807     Document Type: Conference Paper

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