Compressed bit fail maps for memory fail pattern classification

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 17, Issue 3-4, 2001, Pages 291-297

  Vollrath, Jőrg ^a   Lederer, Ulf ^a   Hladschik, Thomas ^a  

^a INFINEON TECHNOLOGIES   (United States)

Author keywords

Bit fail map; Catch ram; Compressed bit fail map; DRAM; Memory

Indexed keywords

AMPLIFIERS (ELECTRONIC); COMPUTER HARDWARE; COMPUTER SOFTWARE; DATA COMPRESSION; DYNAMIC RANDOM ACCESS STORAGE; NUMERICAL METHODS; PATTERN RECOGNITION; STATIC RANDOM ACCESS STORAGE;

BIT FAIL MAPS; CATCH RAM; MEMORY FAIL PATTERN CLASSIFICATION;

INTEGRATED CIRCUIT TESTING;

EID: 0035373127     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1012271530348     Document Type: Article

References (5)

1. Failure analysis of high-density CMOS SRAMs
2. Semiconductor manufacturing process monitoring using built-in self-test for embedded memories
3. Tutorial: SDRAM characterization