Dynamic sparing and error correction techniques for fault tolerance in nanoscale memory structures

2004 4th IEEE Conference on Nanotechnology

Volumn , Issue , 2004, Pages 168-170

  Jeffery, Casey M ^a   Basagalar, Ahmet ^a   Figueiredo, Renato J O ^a  

^a UNIVERSITY OF FLORIDA   (United States)

Author keywords

Memory architecture; Memory fault tolerance; Nanotechnology; Simulation; ULSI

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SIMULATION; DATA STORAGE EQUIPMENT; DIFFERENTIAL EQUATIONS; MATHEMATICAL MODELS; NANOTECHNOLOGY; ULSI CIRCUITS;

DEMULTIPLEXER CIRCUITS; ERROR CORRECTION CODES; MEMORY ARCHITECTURE; MEMORY FAULT TOLERANCE;

FAULT TOLERANT COMPUTER SYSTEMS;

EID: 20344397405     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. C. L. Chen and R. A. Rutledge, "Fault-tolerant memory simulator" IBM J. Res. Develop., vol. 28, no. 2, pp. 184-194, 1984.
2. T. Chen and G. Sunada, "Design of a self-testing and self-repairing structure for highly hierarchical ultra-large capacity memory chips" IEEE Trans. on VLSI Systems, vol. 1, no. 2, pp. 88-97, June 1993.
3. P. J. Kuekes and R. S. Williams, "Demultiplexer for a molecular wire crossbar network" U.S. Patent 6,256,767, July 2001.
4. M. R. Libson and H. E. Harvey, "A general-purpose memory reliability simulator" IBM J. Res. Develop., vol. 28, no. 2, pp. 196-205, 1984.
5. Micron Tech. Inc., "DRAM SER Calculations" 1994.
6. D. A. Patterson, G. Gibson, and R. H. Katz, "A Case for Redundant Arrays of Inexpensive Disks (RAID)" ACM SIGMOD Record, vol. 17, no. 3, pp. 109-116, 1988.
7. A. M. Saleh, J. J. Serrano, and J. H. Patel, "Reliability of scrubbing recovery-techniques for memory systems" IEEE Trans. on Reliab., vol. 39, no. 1, pp. 114-122, April 1998.
8. C. H. Stapper and H. S. Lee, "Synergistic fault-tolerance for memory chips" IEEE Trans. on Computers, vol. 41, no. 9, pp. 1078-1086, September 1992.