A parallel Viterbi decoder for block cyclic and convolution codes

Signal Processing

Volumn 86, Issue 2, 2006, Pages 273-278

  Reeve, J S ^a   Amarasinghe, K ^a  

^a UNIVERSITY OF SOUTHAMPTON   (United Kingdom)

Author keywords

BCH codes; Field programmable gate array; Parallel algorithms; Viterbi decoding

Indexed keywords

CODES (SYMBOLS); DECODING; FIELD PROGRAMMABLE GATE ARRAYS; GRAPH THEORY; PARALLEL ALGORITHMS; SYSTOLIC ARRAYS;

BCH CODES; SYSTOLIC PROCESSORS; TASK GRAPH; VITERBI DECODING;

CONVOLUTION;

EID: 28244490619     PISSN: 01651684     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sigpro.2005.05.016     Document Type: Article

References (11)

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