IntSim: A CAD tool for optimization of multilevel interconnect networks

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2007, Pages 560-567

  Sekar, Deepak C ^a   Naeemi, Azad ^a   Sarvari, Reza ^a   Davis, Jeffrey A ^a   Meindl, James D ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAD TOOLS; CARBON NANOTUBE INTERCONNECTS; CASE STUDIES; CIRCUIT BLOCKS; CO-OPTIMIZATION; COPPER INTERCONNECTS; DIE AREA; DIE SIZE; INTERCONNECT ARCHITECTURES; INTERCONNECT NETWORKS; INTERNATIONAL CONFERENCES; LOW POWERS; MEASURED DATA; P RIOR WORK; SIZE EFFECTS; SYSTEM-LEVEL SIMULATORS; USER INTERFACES; WIRE RESISTIVITY;

CARBON NANOTUBES; COMPUTER SYSTEMS; COPPER; DESIGN; DIES; GRAPHICAL USER INTERFACES; INTEGRATED CIRCUITS; INTERCONNECTION NETWORKS; OPTICAL INTERCONNECTS; OPTIMIZATION;

COMPUTER AIDED DESIGN;

EID: 50249149815     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2007.4397324     Document Type: Conference Paper

References (34)

1. N.S. Nagaraj, W. R. Hunter, P.R. Chidambaram, et al., "Impact of interconnect technology scaling on SOC design methodologies", Proc. Intl. Interconnect Technology Conference, 2005
2. N. Magen, A. Kolodny, U. Weiser, N. Shamir, "Interconnect power dissipation in a microprocessor", Proc. Intl. Workshop on System Level Interconnect Prediction, 2004
3. R. Puri (IBM), "3D design and CAD needs", Proc. SRC Interconnect Forum, Sep. 2006
4. D. Sekar, R. Venkatesan, K. Bowman, et al, "Optimal repeaters for sub-50nm interconnect networks", Proc. Intl. Interconnect Technology Conference, 2006
5. G. Gerosa, S. Gary, C. Dietz, et al, "A 2.2W 80MHz superscalar RISC microprocessor", J. of Solid State Circuits, Dec. 1994
6. W-H. Lee, A. Waite, H. Nii, et al,"High performance 65nm SOI technology with enhanced transistor strain and advanced lowk BEO1,", Proc. Intl. Electron Devices Meeting, 2005
7. C-H. Jan, P. Bai, J. Choi, et al, "A 65nm ultra low power logic platform technology using uni-axial strained silicon transistors", Proc. Intl. Electron Devices Meeting, 2005
8. R. Venkatesan, J. Davis, et al., "Optimal n tier multilevel interconnect architectures for GSI", Trans. VLSI Systems, Dec 2001
9. I. Young, K. Raol, "A comprehensive metric for evaluating interconnect performance", Proc. Intl. Interconnect Technology Conference, 2001
10. J. Warnock, J. Keaty, J. Petrovick, et al, "The circuit and the physical design of the POWER4 microprocessor", IBM J. of R&D, Jan. 2002
11. K. Shakeri, J. Meindl, "Compact physical IR drop models for chip package co-design of GSI", Trans. Electron Devices, Jun. 2005
12. Q. Chen, J. Davis, P. Zarkesh-Ha, J. Meindl, "A compact physical via blockage model", Trans. VLSI Systems, Dec. 2000
13. D. Sekar, E. Demaray, H. Zhang, P. Kohl, et al, "A new global interconnect paradigm: MIM power-ground plane capacitors", Proc. Intl. Interconnect Technology Conference, 2006
14. International Technology Roadmap for Semiconductors
15. M. Lanzerotti, G. Fiorenza, R. Rand, "Assessment of on-chip wire length distribution models", Trans. VLSI Design, Oct. 2004
16. J. Davis, V. De, J. Meindl, "Apriori wiring estimations and optimal multilevel wiring networks for portable ULSI systems", Proc. Electronic Components and Technology Conference, 1996
17. M. Lanzerotti, G. Fiorenza, R Rand, "Interpretation of Rent's rule for ultralarge-scale integrated circuit designs, with an application to wirelength distribution models" Trans. VLSI Design, Dec. 2004.
18. Models in BACPAC: www.eecs.umich.edu/~dennis/bacpac
19. D. Stroobandt, "Apriori wire length estimates for digital design", Kluwer Academic Publishers
20. R. Sarvari, A. Naeemi, P. Zarkesh-Ha, J. Meindl, "Design and optimization for nanoscale power distribution networks in gigascale Systems", Proc. Intl. Interconnect Technology Conference, 2007
21. W. Steinhogl, G. Schindler, et al, "Comprehensive Study of the Resistivity of Copper Wires With Lateral Dimensions of 100 nm and Smaller," J. of Applied Physics, 2005.
22. J. Davis, J. Meindl, "Interconnect technology and design for gigascale integration", Kluwer Academic Publishers
23. G. Chandra, P. Kapur, K. Saraswat, "Scaling trends for the on chip power dissipation", Proc. Intl. Interconnect Technology Conference, 2002
24. K. Banerjee, A. Mehrotra, "A power optimal repeater insertion methodology for global interconnects", Trans. Electron Devices, Nov. 2002.
25. S. Narendra, V. De, S. Borkar, D. Antoniadis, A. Chandrakasan, "Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18um CMOS," J. of Solid State Circuits, Mar. 2004.
26. N. Sakran, M. Yuffe, M. Mehalel, J. Doweck, E. Knoll, A. Kovacs, "The implementation of the 65nm dual core Merom processor", Proc. Intl. Solid State Circuits Conference, 2007
27. 2 SRAM cell", Proc. Intl. Electron Devices Meeting, 2004
28. S. Naffziger, B. Stackhouse, T. Grutkowski, "The implementation of a 2 core multi-threaded Itanium family processor", Proc. Intl. Solid State Circuits Conference, 2005
29. R. Sarvari, A. Naeemi, and James. D. Meindl, "Impact of size effects on the resistivity of copper wires and consequently the design and performance of metal interconnect networks", Proceedings Intl. Interconnect Technology Conference, 2005
30. A. Naeemi, J. Meindl, "Compact physical models for multiwall carbon nanotube interconnects", Electron Device Letters, May 2006
31. A. Naeemi, J. Meindl, "Design and performance modeling for single walled CNTs as local, semiglobal and global interconnects in gigascale integrated systems", Trans. Electron Devices, Jan. 2007
32. S. Sato, M. Nihei, "Novel approach to fabricating carbon nanotube via interconnects using size-controlled catalyst nanoparticles", Proc. Intl. Interconnect Technology Conf, 2006
33. H. Li, W. Lu, J. Li, et al, "Multichannel ballistic transport in multiwall carbon nanotubes", Phy. Review Letters, Aug. 2005
34. A. Naeemi, R. Sarvari, J. Meindl, "Performance modeling and optimization for single and multiwall carbon nanotube interconnects", Proc. Design Automation Conference, 2007