Optimal repeaters for sub-50nm interconnect networks

2006 International Interconnect Technology Conference, IITC

Volumn , Issue , 2006, Pages 199-201

  Sekar, Deepak C ^a   Venkatesan, Raguraman ^b   Bowman, Keith A ^b   Joshi, Ajay ^a   Davis, Jeffrey A ^a   Meindl, James D ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; COMBINATIONAL LOGICS; INTERCONNECT NETWORKS; INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE; LOW POWERS; REPEATER INSERTION; SUB-50 NM; TOTAL POWER;

TECHNOLOGY;

EID: 50249188385     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2006.1648687     Document Type: Conference Paper

References (10)

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4. R. Venkatesan, et al, Trans. VLSI Syst., Dec. 2001
5. D. Sylvester, "BACPAC" www.eecs.umich.edu/~dennisacpac/ bacpac_models.html
6. Berkeley Predictive Technology Model website (BPTM)
7. G. Garcea, et al., Proc. ICCAD'03
8. K.Banerjee, et al., Proc. IEEE, pp.602-633, May 2001
9. A. Rahman, R.Reif, Proc. IITC'01
10. P. Morrow, et al, Proc. AMC'04