A 65nm ultra low power logic platform technology using uni-axial strained silicon transistors

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 2005, Issue , 2005, Pages 60-63

  Jan, C H ^a   Bai, P ^a   Choi, J ^a   Curello, G ^a   Jacobs, S ^a   Jeong, J ^a   Johnson, K ^a   Jones, D ^a   Klopcic, S ^a   Lin, J ^a   Lindert, N ^a   Lio, A ^a   Natarajan, S ^a   Neirynck, J ^a   Packan, P ^a   Park, J ^a   Post, I ^a   Patel, M ^a   Ramey, S ^a   Reese, P ^a   Rockford, L ^a   Roskowski, A ^a   Sacks, G ^a   Turkot, B ^a   Wang, Y ^a   Wei, L ^a   Yip, J ^a   Young, I ^a   Zhang, K ^a   Zhang, Y ^a   Bohr, M ^a   Holt, B ^a   more..

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LEAKAGE CURRENTS; LOGIC DEVICES; MOS DEVICES; SILICON; STATIC RANDOM ACCESS STORAGE;

CELL STANDBY LEAKAGE; LEAKAGE SUPPRESSION; SILICON TRANSISTORS; SLEEP TRANSISTORS;

FIELD EFFECT TRANSISTORS;

EID: 33845988529     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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