Polaris: A system-level roadmap for on-chip interconnection networks

IEEE International Conference on Computer Design, ICCD 2006

Volumn , Issue , 2006, Pages 134-141

  Soteriou, Vassos ^a   Eisley, Noel ^a   Wang, Hangsheng ^b   Li, Bin ^a   Peh, Li Shiuan ^a  

^a PRINCETON UNIVERSITY   (United States)

^b FREESCALE SEMICONDUCTOR INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH NETWORKS; CHIP MULTI-PROCESSORS; COMPUTER DESIGNS; DEMANDING APPLICATIONS; DESIGN PROCESSES; FEATURE SIZES; INTERNATIONAL CONFERENCES; MULTI-PROCESSOR SYSTEMS; NETWORK DESIGNS; NETWORK TRAFFICS; NOC ARCHITECTURES; NOC DESIGN; NOC SYNTHESIS; ON CHIPS; ON-CHIP COMMUNICATIONS; ON-CHIP INTERCONNECTION NETWORKS; POLARIS; PROCESS CHARACTERISTICS; ROAD MAPPING; ROAD MAPS; RUN-TIME; SYSTEM DESIGNERS; SYSTEM LEVELS; TECHNOLOGY TRENDS;

ARCHITECTURE; COMPLEXATION; COMPUTER SYSTEMS; COST EFFECTIVENESS; ELECTRIC NETWORK TOPOLOGY; INTERCONNECTION NETWORKS; INTERNET; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; PROCESS DESIGN; PROCESS ENGINEERING; REAL TIME SYSTEMS; ROUTERS; TECHNOLOGY; TELECOMMUNICATION NETWORKS;

SOFTWARE DESIGN;

EID: 49849091093     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2006.4380806     Document Type: Conference Paper

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