A processor-based built-in self-repair design for embedded memories

Proceedings of the Asian Test Symposium

Volumn 2003-January, Issue , 2003, Pages 366-371

  Su, Chin Lung ^a   Huang, Rei Fu ^a   Wu, Cheng Wen ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BUILT-IN SELF TEST; DESIGN; MEMORY ARCHITECTURE; MICROPROCESSOR CHIPS; PRODUCT DESIGN; PROGRAMMABLE LOGIC CONTROLLERS; REDUNDANCY; REPAIR; STATIC RANDOM ACCESS STORAGE; SYSTEM-ON-CHIP;

AT-SPEED TESTING; BUILT IN SELF REPAIRS; DESIGN FLEXIBILITY; EMBEDDED MEMORY; EMBEDDED PROCESSORS; REDUNDANCY ANALYSIS; SYSTEM-ON-CHIP PRODUCTS; TEST ALGORITHMS;

INTEGRATED CIRCUIT DESIGN;

EID: 84954455193     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ATS.2003.1250838     Document Type: Conference Paper

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