A generalization of the single b-Bit byte error correcting and double bit error detecting codes for high-speed memory systems

IEEE Transactions on Computers

Volumn 45, Issue 4, 1996, Pages 508-511

  Xiao, Sihai ^a   Shi, Xiaofa ^a   Feng, Guiliang ^a   Rao, T R N ^a  

^a UNIVERSITY OF LOUISIANA AT LAFAYETTE   (United States)

Author keywords

Byte error correcting detecting codes; Companion matrix; High speed memories; Primitive polynomials; Subfields cosets

Indexed keywords

EID: 33747479094     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.494112     Document Type: Article

References (6)

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2. C.L. Chen, "Error Correcting Codes with Byte Error-Detection Capability," IEEE Trans. Computers, vol. 32, no. 7, pp. 615-621, July 1983.
3. R.H. Deng and D.J. Costello Jr., "Decoding of DBEC-TBED Reed-Solomon Codes," IEEE Trans. Computers, vol. 36, no. 11, pp. 1,359-1,363, Nov. 1987.
4. S.J. Hong and A.M. Patel, "A General Class of Maximal Codes for Computer Applications," IEEE Trans. Computers, vol. 21, no. 12, pp. 1,322-1,331, Dec. 1972.
5. T.R.N. Rao and E. Fijiwara, Error-Control Coding for Computer Systems. Englewood Cliffs, N.J.: Prentice Hall, 1989.
6. A.M. Patel, "Error Recovery Scheme for the IBM 3850 Mass Storage System," IBM J. Research and Development, vol. 24, no. 1, pp. 32-42, 1980.