Redundancy, repair, and test features of a 90nm embedded SRAM generator

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn 2003-January, Issue , 2003, Pages 467-474

  Aitken, Rob ^a   Dogra, Neeraj ^a   Gandhi, Dhrumil ^a   Becker, Scott ^a  

^a Artisan Components   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DEFECTS; FAULT TOLERANCE; MEMORY ARCHITECTURE; PROGRAMMABLE LOGIC CONTROLLERS; REDUNDANCY; REPAIR; STATIC RANDOM ACCESS STORAGE; SYSTEM-ON-CHIP;

EMBEDDED MEMORY; EMBEDDED SRAM; SYSTEM ON CHIP DESIGN; TESTABILITY;

DESIGN FOR TESTABILITY;

EID: 84964931717     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TSM.2005.1250145     Document Type: Conference Paper

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