Optimal spare utilization in repairable and reliable memory cores

Records of the IEEE International Workshop on Memory Technology, Design and Testing

Volumn 2003-January, Issue , 2003, Pages 64-71

  Choi, M ^a   Park, N ^b   Lombardi, F ^c   Kim, Y B ^c   Piuri, V ^d  

^a MISSOURI UNIVERSITY OF SCIENCE AND TECHNOLOGY   (United States)

^b Department of Computer Science   (United States)

^c NORTHEASTERN UNIVERSITY   (United States)

^d UNIVERSITY OF MILAN   (Italy)

Author keywords

Built In Self Repair; Embedded Memory Repair and Reliability; Fault Tolerant Memory Core; System on chip; Yield.

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BUILT-IN SELF TEST; DEFECTS; EMBEDDED SYSTEMS; EQUIPMENT TESTING; FAULT TOLERANCE; LEGACY SYSTEMS; LOGIC DEVICES; MANUFACTURE; MEMORY ARCHITECTURE; MICROPROCESSOR CHIPS; MULTICHIP MODULES; PRINTED CIRCUIT BOARDS; PRINTED CIRCUITS; PROGRAMMABLE LOGIC CONTROLLERS; REDUNDANCY; RELIABILITY; REPAIR;

AUTOMATED TEST EQUIPMENT; BUILT IN SELF REPAIRS; DEFECT AND FAULT TOLERANCES; EMBEDDED MEMORY; HIGH PERFORMANCE SYSTEMS; MEMORY CORE; SYSTEM-ON-CHIP TECHNOLOGY; YIELD;

SYSTEM-ON-CHIP;

EID: 51549091201     PISSN: 10874852     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MTDT.2003.1222363     Document Type: Conference Paper

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