Explicit gate delay model for timing evaluation

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2003, Pages 32-38

  Shao, Muzhou ^a   Wong, Martin D F ^b   Cao, Huijing ^c   Gao, Youxin ^d   Yuan, Li Pen ^d   Huang, Li Da ^a   Lee, Seokjin ^a  

^a University of Texas at Austin   (United States)

^b UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^c Motorola China Research Center   (China)

^d SYNOPSYS INC   (United States)

Author keywords

Explicit; Gate delay model; Pre characterize

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER SIMULATION; GATES (TRANSISTOR); ITERATIVE METHODS; TOPOLOGY;

GATE DELAY MODELS;

VLSI CIRCUITS;

EID: 0038040894     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/640006.640010     Document Type: Conference Paper

References (18)

1. Ravishankar Arunachalam, Florentin Dartu, Lawrence T. Pileggi, "CMOS Gate Delay Models for General RLC Loading", Proceedings of ICCD '97, pp. 224-229, 1997.
2. Avant! Corporation. "Star-Hspice Manual", Release 1998.2, July 1998.
3. Florentin Dartu, Noel Menezes, Jessica Qian, Lawrence T. Pillage, "A gate-delay model for high-speed CMOS circuits", 31st ACM/IEEE DAC, pp. 576-580, 1994.
4. Florentin Dartu, Noel Menezes, Lawrence T. Pillage, "Performance Computation for precharacterized CMOS Gate with RC Load", IEEE Trans. on Computer-Aided Design of Integrated Circuits and System, Vol. 15, pp. 544-553, 1996.
5. Florentin Dartu, Lawrence T. Pileggi, "Calculating worst-case gate delays due to dominant capacitance coupling" 34th ACM/IEEE DAC, pp. 46 - 51, 1997.
6. Anirudth Devgan and Peter R. O'Brien, "Realizable reduction for RC interconnect circuits", IEEE/ACM International Conference on Computer-Aided Design , pp. 204-207, 1999.
7. Peter Feldmann and Roland W. Freund, "Efficient linear circuit analysis by Pade approximation via the Lanczos process", IEEE Trans. on Computer-Aided Design of Intergrated Circuits and System, Vol. 14, pp. 639-649, 1995.
8. Andrew B. Kahng and Sudhakar Muddu, "Improved effective capacitance computations for use in logic and layout optimization", Proceedings of Twelfth International Conference On VLSI Design, pp. 578-582, 1999.
9. Andrew B. Kahng and Sudhakar Muddu, "New Efficient Algorithms for Computing Effective Capacitance", Proceedings of ACM/IEEE International Symposium on Physical Design, pp. 147-151, 1998.
10. Chandramouli V. Kashyap and Byron L. Krauter, "A realizable driving point model for on-chip interconnect with inductance", 37th ACM/IEEE DAC, pp. 190-195, 2000.
11. Alexander Korshak and Jyh-Chwen Lee, "An effective current source cell model for VDSM delay calculation", 2001 International Symposium on Quality Electronic Design, pp. 296-300, 2001.
12. Peter R. O'Brien and Thomas L. Savarino, "Modeling the driving-point characteristic of resistive interconnect for accurate delay estimation", IEEE/ACM International Conference on Computer-Aided Design, pp. 512-515, 1989.
13. Lawrence T. Pillage and Ronald A. Rohrer, "Asymptotic waveform evaluation for timing analysis", IEEE Trans. on Computer-Aided Design of Integrated Circuits and System, Vol. 9, pp. 352-366, 1990.
14. Jessica Qian, Satyamurthy Pullela, Lawrence T. Pillage, "Modeling the "Effective capacitance" for the RC interconnect of CMOS gates", IEEE Trans. on Computer-Aided Design of Integrated Circuits and System, Vol. 13, pp. 1526-1535, 1994.
15. Curtis L. Ratzlaff and Lawrence T. Pillage, "RICE: rapid interconnect circuit evaluation using AWE", IEEE Trans. on Computer-Aided Design of Intergrated Circuits and System, Vol. 13, pp. 763-776, 1994.
16. Curtis L. Ratzlaff, Satyamurthy Pullela, Lawrence T. Pillage, "Modeling The RC-interconnect Effects In A Hierarchical Timing Analyzer", Proceedings IEEE Custom Intergrated Circuits Conference, pp. 15.6.1-15.6.4, 1992.
17. Semiconductor Industry Association, "International Technology Roadmap for Semiconductors 2001 Edition", 2002.
18. Semiconductor Industry Association, "International Technology Roadmap for Semiconductors 2000 Update", 2000.