Adaptive routing strategies for fault-tolerant on-chip networks in dynamically reconfigurable systems

IET Computers and Digital Techniques

Volumn 2, Issue 3, 2008, Pages 184-198

  Nunez Yanez, J L ^a   Edwards, D ^b   Coppola, A M ^c  

^a UNIVERSITY OF BRISTOL   (United Kingdom)

^b UNIVERSITY OF MANCHESTER   (United Kingdom)

^c STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK TOPOLOGY; EMBEDDED SYSTEMS; FAULT TOLERANCE; MANUFACTURE; PARALLEL PROCESSING SYSTEMS; QUALITY ASSURANCE; RELIABILITY;

(100) SILICON; (OTDR) TECHNOLOGY; (PL) PROPERTIES; ADAPTIVE ROUTING; ASYNCHRONOUS NETWORKS; DEEP SUB-MICRON (DSM); DETERMINISTIC ROUTING; DYNAMICALLY RECONFIGURABLE SYSTEMS (DRS); FAULT TOLERANCES; FAULT-TOLERANT; FEATURE SIZES; HIGH PERFORMANCE; LOW-COMPLEXITY; MULTI CORE SYSTEMS; MULTI PROCESSOR SYSTEMS; ON CHIP COMMUNICATIONS; ON CHIP NETWORK (OCN); RE CONFIGURABLE COMPUTING (RCC);

ADAPTIVE SYSTEMS;

EID: 46649109921     PISSN: 17518601     EISSN: None     Source Type: Journal    
DOI: 10.1049/iet-cdt:20060175     Document Type: Article

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