Toward an integrated design methodology for fault-tolerant, multiple clock/voltage integrated systems

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2004, Pages 168-173

  Marculescu, Radu ^a   Marculescu, Diana ^a   Pileggi, Larry ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MICROARCHITECTURES; MULTIPLE CLOCK/VOLTAGE (MCV); POWER EFFICIENCY; SPEED SCALING;

ELECTRIC POTENTIAL; ENERGY EFFICIENCY; ERROR ANALYSIS; FAULT TOLERANT COMPUTER SYSTEMS; MATHEMATICAL MODELS; ROUTERS;

INTEGRATED CIRCUIT LAYOUT;

EID: 17644388874     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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