The design and test of a smartcard chip using a CHAIN self-timed network-on-chip

Proceedings -Design, Automation and Test in Europe, DATE

Volumn 3, Issue , 2004, Pages 274-279

  Bainbridge, W J ^a   Plana, L A ^a   Furber, S B ^a  

^a UNIVERSITY OF MANCHESTER   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN AND TESTS; HIGH FREQUENCY HF; NETWORK ON CHIP; NETWORK-ON-CHIP ARCHITECTURES; SERIAL COMMUNICATIONS; SMART-CARD CHIPS; TESTING AND DEBUGGING; TIMING ANALYSIS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CHAINS; CLOCKS; EXHIBITIONS; PROGRAMMABLE LOGIC CONTROLLERS; SERVERS; SMART CARDS; VLSI CIRCUITS;

DESIGN;

EID: 84893792127     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1269249     Document Type: Conference Paper

References (11)

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