On the use of yielded cost in modelling electronic assembly processes

IEEE Transactions on Electronics Packaging Manufacturing

Volumn 24, Issue 3, 2001, Pages 195-202

  Backer, Daniel V ^b   Sandborn, Peter A ^a,b  

^a IEEE

^b UNIVERSITY OF MARYLAND   (United States)

Author keywords

Cost; Design to cost; Rework; Test economics; Yield; Yielded cost

Indexed keywords

ASSEMBLY; ELECTRONICS PACKAGING; ITERATIVE METHODS; MATHEMATICAL MODELS;

ELECTRONIC ASSEMBLY PROCESSES;

ELECTRON DEVICE MANUFACTURE;

EID: 0035401602     PISSN: 1521334X     EISSN: None     Source Type: Journal    
DOI: 10.1109/6104.956805     Document Type: Article

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