Procedures for identifying untestable and redundant transition faults in synchronous sequential circuits

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2003, Pages 36-41

  Chen, Gang ^a   Reddy, Sudhakar M ^a   Pomeranz, Irith ^b  

^a UNIVERSITY OF IOWA   (United States)

^b PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FAILURE ANALYSIS; INTEGRATED CIRCUIT TESTING; ITERATIVE METHODS; LOGIC CIRCUITS; OPTIMIZATION;

DELAY DEFECTS; TRANSITION FAULTS;

SEQUENTIAL CIRCUITS;

EID: 0344119506     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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