A two-step-recess process based on atomic-layer etching for high-performance In0.52Al0.48As/In0.53 Ga0.47As p-HEMTs

IEEE Transactions on Electron Devices

Volumn 55, Issue 7, 2008, Pages 1577-1584

  Kim, Tae Woo ^a   Kim, Dae Hyun ^b   Park, Sang Duk ^c   Shin, Seung Heon ^a   Jo, Seong June ^a   Song, Ho Jin ^a   Park, Young Min ^d,e   Bae, Jeoun Oun ^c   Kim, Young Woon ^d   Yeom, Geun Young ^c   Jang, Jae Hyung ^a   Song, Jong In ^a  

^a Gwangju Institute of Science and Technology (GIST)   (South Korea)

^b Massachusetts Institute of Technology Cambridge   (United States)

^c Sungkyunkwan University   (South Korea)

^d Seoul National University   (South Korea)

^e STANFORD UNIVERSITY   (United States)

Author keywords

Atomic layer etching (ALET); Channel electron saturation velocity (vsat); Gate recess process; Pseudomorphic high electron mobility transistor (p HEMT)

Indexed keywords

(E ,3E) PROCESS;

EID: 46649103444     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2008.923522     Document Type: Article

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