Effect of a two-step recess process using atomic layer etching on the performance of In0.52Al0.48As/In0.53 Ga0.47As p-HEMTs

IEEE Electron Device Letters

Volumn 28, Issue 12, 2007, Pages 1086-1088

  Kim, Tae Woo ^a   Kim, Dae Hyun ^b   Park, Sang Duk ^c   Yeom, Geun Young ^c   Lim, Byeong Ok ^d   Rhee, Jin Koo ^d   Jang, Jae Hyung ^a   Song, Jong In ^a  

^a Gwangju Institute of Science and Technology (GIST)   (South Korea)

^b Massachusetts Institute of Technology Cambridge   (United States)

^c Sungkyunkwan University   (South Korea)

^d Dongguk University   (South Korea)

Author keywords

Atomic layer deposition; Atomic layer etching (ALET); drain induced barrier lowering (DIBL); Electron mobility; HEMT circuits; High electron mobility transistors; ION IOFF ratio; Pseudomorphic high electron mobility transistor (p HEMT); Subthreshold slope

Indexed keywords

ATOMIC LAYER DEPOSITION; ELECTRON MOBILITY; REACTIVE ION ETCHING; THRESHOLD VOLTAGE;

DRAIN-INDUCED BARRIER LOWERING; PLASMA-INDUCED DAMAGE; SUBTHRESHOLD SLOPE;

HIGH ELECTRON MOBILITY TRANSISTORS;

EID: 36549075548     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2007.910278     Document Type: Article

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