100-Gb/s multiplexing and demultiplexing IC operations in InP HEMT technology

IEEE Journal of Solid-State Circuits

Volumn 39, Issue 1, 2004, Pages 207-213

  Murata, Koichi ^a   Sano, Kimikazu ^a   Kitabayashi, Hiroto ^a   Sugitani, Suehiro ^a   Sugahara, Hirohiko ^a   Enoki, Takatomo ^a  

^a NTT CORPORATION   (Japan)

Author keywords

D type flip flop; Error free operation; High speed digital integrated circuit; InP HEMT; Optical fiber communications; Selector circuit

Indexed keywords

BIT ERROR RATE; DEMULTIPLEXING; FLIP FLOP CIRCUITS; GATES (TRANSISTOR); INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUIT TESTING; MULTIPLEXING; OPTICAL COMMUNICATION; SEMICONDUCTING INDIUM PHOSPHIDE;

D-TYPE FLIP FLOP; EYE DIAGRAMS; SELECTOR INTEGRATED CIRCUITS;

HIGH ELECTRON MOBILITY TRANSISTORS;

EID: 0742303633     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.820854     Document Type: Article

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