Highly selective and low damage atomic layer etching of InPInAlAs heterostructures for high electron mobility transistor fabrication

Applied Physics Letters

Volumn 91, Issue 1, 2007, Pages

  Park, S D ^a   Oh, C K ^a   Lim, W S ^a   Lee, H C ^a   Bae, J W ^a   Yeom, G Y ^a,c   Kim, T W ^b   Song, J I ^b   Jang, J H ^b  

^a Sungkyunkwan University   (South Korea)

^b Gwangju Institute of Science and Technology (GIST)   (South Korea)

^c National Program for Tera Level Devices   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ATOMIC LAYER ETCHING (ALET) TECHNOLOGY; DRY GATE RECESS; ELECTRICAL CHARACTERISTICS; STOICHIOMETRIC MODIFICATION;

HETEROJUNCTIONS; PLASMA ETCHING; SCHOTTKY BARRIER DIODES; STOICHIOMETRY; SURFACE CHEMISTRY; X RAY PHOTOELECTRON SPECTROSCOPY;

HIGH ELECTRON MOBILITY TRANSISTORS;

EID: 34548475816     PISSN: 00036951     EISSN: None     Source Type: Journal    
DOI: 10.1063/1.2754636     Document Type: Article

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