High-performance 0.1-μm gate enhancement-mode InAlAs/InGaAs HEMT's using two-step recessed gate technology

IEEE Transactions on Electron Devices

Volumn 46, Issue 6, 1999, Pages 1074-1080

  Suemitsu, Tetsuya ^a   Yokoyama, Haruki ^a   Umeda, Yohtaro ^a   Enoki, Takatomo ^a   Ishii, Yasunobu ^a  

^a NTT CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ARGON; ELECTRIC RESISTANCE; GATES (TRANSISTOR); PLASMA ETCHING; SEMICONDUCTING INDIUM COMPOUNDS; SEMICONDUCTOR DEVICE MANUFACTURE; THRESHOLD VOLTAGE; TRANSCONDUCTANCE;

CUTOFF FREQUENCY; ETCHING SELECTIVITY; GATE RECESS ETCHING; PARASITIC RESISTANCE; RECESS STOPPING LAYER; SIDE ETCHING; TWO STEP RECESSED GATE TECHNOLOGY;

HIGH ELECTRON MOBILITY TRANSISTORS;

EID: 0032663797     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.766866     Document Type: Article

References (27)