CLIPPER: Counter-based low impact processor power estimation at run-time

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2007, Pages 890-895

  Peddersen, Jorgen ^a   Parameswaran, Sri ^a  

^a UNIVERSITY OF NEW SOUTH WALES   (Australia)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS; ELECTRIC CURRENT MEASUREMENT; ELECTRIC POWER MEASUREMENT; EMBEDDED SYSTEMS; ENERGY MANAGEMENT; INDUSTRIAL ENGINEERING; INDUSTRIAL MANAGEMENT; MECHANIZATION; OPTIMIZATION;

APPLIED (CO); AVERAGE POWER; AVERAGE POWER CONSUMPTIONS; CASE STUDIES; DESIGN AUTOMATION CONFERENCE (DAC); DYNAMIC POWER; DYNAMIC POWER MANAGEMENT (DPM); EFFICIENT METHODS; EMBEDDED DESIGNS; ENERGY ESTIMATION; IN-CHIP; MEASUREMENT SYSTEMS; NOVEL METHODOLOGY; PERFORMANCE COUNTERS; POWER OPTIMIZATION; PROCESSOR POWER; RUN TIME; RUN-TIME OPTIMIZATION; SOUTH PACIFIC;

ESTIMATION;

EID: 46649088350     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2007.358102     Document Type: Conference Paper

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