A hybrid approach for core-based system-level power modeling

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2000, Pages 141-145

  Givargis, Tony ^a   Vahid, Frank ^a   Henkel, Jörg ^b  

^a University of California Riverside   (United States)

^b NEC LABORATORIES AMERICA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ABSTRACTION LEVEL; HIGH-LEVEL MODELS; POWER ESTIMATIONS; REGISTER TRANSFER LEVEL; SIMULATION SPEED-UP; SYSTEM LEVEL DESIGN; SYSTEM-LEVEL MODELING; SYSTEM-ON-A-CHIP DESIGNS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; TABLE LOOKUP;

DISPENSERS;

EID: 84884690219     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/368434.368593     Document Type: Conference Paper

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