Run-time energy estimation in system-on-a-chip designs

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2003-January, Issue , 2003, Pages 595-599

  Haid, J ^a   Kaefer, G ^a   Steger, Ch ^a   Weiss, R ^a  

^a GRAZ UNIVERSITY OF TECHNOLOGY   (Austria)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; DESIGN; MICROPROCESSOR CHIPS; MOTION PICTURE EXPERTS GROUP STANDARDS; PROGRAMMABLE LOGIC CONTROLLERS;

ENERGY ESTIMATION; ESTIMATION PROCESS; FUNCTIONAL UNITS; MAXIMUM RELATIVE ERRORS; MEASUREMENT EQUIPMENT; POWER OPTIMIZATION; SAMPLING-BASED PROFILING; SYSTEM-ON-A-CHIP DESIGNS;

SYSTEM-ON-CHIP;

EID: 84954435520     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2003.1195094     Document Type: Conference Paper

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