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Volumn , Issue , 2005, Pages 111-116

Rapid embedded hardware/software system generation

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; C (PROGRAMMING LANGUAGE); COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER SOFTWARE; PROGRAM PROCESSORS;

EID: 27644466199     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (28)

References (26)
  • 2
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    • Tensilica Inc.
    • "Xtensa Processor." Tensilica Inc. (http://www.tensilica.com).
    • Xtensa Processor
  • 3
    • 27944509298 scopus 로고    scopus 로고
    • ARC International
    • "ARCtangent." ARC International (http://www.arc.com).
    • ARCtangent
  • 4
    • 27944463767 scopus 로고    scopus 로고
    • Improv Inc.
    • "Jazz DSP." Improv Inc. (http://www.improvsys.com).
    • Jazz DSP
  • 5
    • 84881111915 scopus 로고    scopus 로고
    • Altera Corp.
    • "Altera Nios Processor." Altera Corp. (http://www.altera.com).
    • Altera Nios Processor
  • 6
    • 27944467613 scopus 로고    scopus 로고
    • 3DSP Corp.
    • "SP-5flex." 3DSP Corp. (http://www.3dsp.com).
    • SP-5flex
  • 7
    • 84893735242 scopus 로고    scopus 로고
    • Rapid configuration & instruction selection for an ASIP: A case study
    • (Messe Munich, Germany), IEEE Computer Society, Los Alamitos, California
    • N. Cheung, J. Henkel, and S. Parameswaran, "Rapid configuration & instruction selection for an ASIP: A case study," in DATE'03, (Messe Munich, Germany), pp. 802-807, IEEE Computer Society, Los Alamitos, California, 2003.
    • (2003) DATE'03 , pp. 802-807
    • Cheung, N.1    Henkel, J.2    Parameswaran, S.3
  • 9
    • 3042558095 scopus 로고    scopus 로고
    • MINCE: Matching instructions using combinational equivalence for extensible processor
    • (CNIT La Dfense, Paris, France), IEEE Computer Society, Los Alamitos, California
    • N. Cheung, S. Parameswaran, J. Henkel, and J. Chan, "MINCE: Matching instructions using combinational equivalence for extensible processor," in DATE'04, vol. 2, (CNIT La Dfense, Paris, France), pp. 1020-1025, IEEE Computer Society, Los Alamitos, California, 2004.
    • (2004) DATE'04 , vol.2 , pp. 1020-1025
    • Cheung, N.1    Parameswaran, S.2    Henkel, J.3    Chan, J.4
  • 11
    • 2342501770 scopus 로고    scopus 로고
    • Synthesis-driven exploration of pipelined embedded processors
    • P. Mishra, A. Kejariwal, and N. Dutt, "Synthesis-driven exploration of pipelined embedded processors," in VLSID'04, pp.921-926, 2004.
    • (2004) VLSID'04 , pp. 921-926
    • Mishra, P.1    Kejariwal, A.2    Dutt, N.3
  • 12
    • 0036469652 scopus 로고    scopus 로고
    • SimpleScalar: An infrastructure for computer system modeling
    • T. Austin, E. Larson, and D. Ernst, "SimpleScalar: an infrastructure for computer system modeling," Computer, vol. 35, no. 2, pp. 59-67, 2002.
    • (2002) Computer , vol.35 , Issue.2 , pp. 59-67
    • Austin, T.1    Larson, E.2    Ernst, D.3
  • 15
    • 27944507019 scopus 로고    scopus 로고
    • Application to silicon: Understanding the improv methodology
    • Improv Systems Inc., June
    • "Application to silicon: Understanding the improv methodology," white paper, Improv Systems Inc., June 2001.
    • (2001) White Paper
  • 16
    • 84893770247 scopus 로고    scopus 로고
    • ASIP Meister
    • "ASIP Meister." ASIP Meister (http://www.edameister.org/asip- meister).
    • ASIP Meister
  • 17
    • 0141788669 scopus 로고    scopus 로고
    • Rapid prototyping of JPEG encoder using the ASIP development system: PEAS-III
    • S. Kobayashi, K. Mita, Y. Takeuchi, and M. Imai, "Rapid prototyping of JPEG encoder using the ASIP development system: PEAS-III," in ICASSP, vol. 2, pp. 485-488, 2003.
    • (2003) ICASSP , vol.2 , pp. 485-488
    • Kobayashi, S.1    Mita, K.2    Takeuchi, Y.3    Imai, M.4
  • 20
    • 84893597192 scopus 로고    scopus 로고
    • EXPRESSION: A language for architecture exploration through compiler/simulator retargetability
    • Munich, Germany
    • A. Halambi, P. Grun, V. Ganesh, A. Khare, N. Dutt, and A. Nicolau, "EXPRESSION: a language for architecture exploration through compiler/simulator retargetability," in DATE'99, (Munich, Germany), pp. 485-490, 1999.
    • (1999) DATE'99 , pp. 485-490
    • Halambi, A.1    Grun, P.2    Ganesh, V.3    Khare, A.4    Dutt, N.5    Nicolau, A.6
  • 21
    • 84941269625 scopus 로고    scopus 로고
    • Rapid exploration of pipelined processors through automatic generation of synthesizable rtl models
    • P. Mishra, A. Kejariwal, and N. Dutt, "Rapid exploration of pipelined processors through automatic generation of synthesizable rtl models," in Workshop of Rapid System Prototyping (RSP), 2003.
    • (2003) Workshop of Rapid System Prototyping (RSP)
    • Mishra, P.1    Kejariwal, A.2    Dutt, N.3
  • 23
    • 27944481457 scopus 로고    scopus 로고
    • HDLGen: Architecture description language driven HDL generation for pipelined processors
    • Center for Embedded Computer Systems, University of California, Irvine, CA 92697, USA, February
    • A. Kejariwal, P. Mishra, J. Astrom, and N. Dutt, "HDLGen: Architecture description language driven HDL generation for pipelined processors," technical report, Center for Embedded Computer Systems, University of California, Irvine, CA 92697, USA, February 2003.
    • (2003) Technical Report
    • Kejariwal, A.1    Mishra, P.2    Astrom, J.3    Dutt, N.4
  • 26
    • 27944491706 scopus 로고    scopus 로고
    • Synopsys Design Compiler
    • "Synoposys Design Compiler." Synopsys Design Compiler (http://www.synopsys.com).
    • Synoposys Design Compiler


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.